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DRV8813 www.ti.com slvsa72c C april 2010 C revised may 2011 dual-bridge motor controller ic check for samples: DRV8813 1 features applications 2 ? dual-h-bridge current-control motor driver ? automatic teller machines C capable of driving a bipolar stepper or ? money handling machines two dc motors ? video security cameras C two-bit winding current control allows up ? printers to four current levels ? scanners C low mosfet on-resistance ? office automation machines ? 2.5-a maximum drive current at 24 v, 25 c ? gaming machines ? built-in 3.3-v reference output ? factory automation ? industry-standard parallel digital control ? robotics interface ? 8.2-v to 45-v operating supply voltage range ? thermally enhanced surface mount package description the DRV8813 provides an integrated motor driver solution for printers, scanners, and other automated equipment applications. the device has two h-bridge drivers, and can drive a bipolar stepper motor or two dc motors. the output driver block for each consists of n-channel power mosfet s configured as full h-bridges to drive the motor windings. the DRV8813 can supply up to 2.5-a peak or 1.75-a rms output current (with proper heatsinking at 24 v and 25 c). a simple parallel digital control interface is compatible with industry-standard devices. decay mode is programmable. internal shutdown functions are provided for over current protection, short circuit protection, under voltage lockout and overtemperature. the DRV8813 is available in a 28-pin htssop package with powerpad ? (eco-friendly: rohs & no sb/br). ordering information (1) orderable part top-side t a package (2) number marking C 40 c to 85 c powerpad ? (htssop) - pwp reel of 2000 DRV8813pwpr 8813 (1) for the most current packaging and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . (2) package drawings, thermal data, and symbolization are available at www.ti.com/packaging . 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 powerpad is a trademark of texas instruments. production data information is current as of publication date. copyright ? 2010 C 2011, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
DRV8813 slvsa72c C april 2010 C revised may 2011 www.ti.com device information functional block diagram 2 copyright ? 2010 C 2011, texas instruments incorporated charge pump thermal shut down aout1 aout2 bout1 bout2 gnd gnd 0.1 m f 0.01 m f vm step motor vma vmb cp1 cp2 vcp isena isenb aenbl ai0 bphase benbl avref hs gate drive vm vm internal reference & regs int. vcc motor driver b nfault control logic nreset motor driver a aphase nsleep vm v3p3out 3.3v ls gate drive + + - - 3.3 v bvref ai1 bi0 bi1 dcm dcm vm decay
DRV8813 www.ti.com slvsa72c C april 2010 C revised may 2011 table 1. terminal functions external components name pin i/o (1) description or connections power and ground gnd 14, 28 - device ground vma 4 - bridge a power supply connect to motor supply (8.2 - 45 v). both pins must be connected to same supply. vmb 11 - bridge b power supply bypass to gnd with a 0.47- f 6.3-v ceramic v3p3out 15 o 3.3-v regulator output capacitor. can be used to supply vref. cp1 1 io charge pump flying capacitor connect a 0.01- f 50-v capacitor between cp1 and cp2. cp2 2 io charge pump flying capacitor connect a 0.1- f 16-v ceramic capacitor to vcp 3 io high-side gate drive voltage vm. control logic high to enable bridge a. internal aenbl 21 i bridge a enable pulldown. logic high sets aout1 high, aout2 low. aphase 20 i bridge a phase (direction) internal pulldown. ai0 24 i sets bridge a current: 00 = 100%, bridge a current set 01 = 71%, 10 = 38%, 11 = 0 ai1 25 i internal pulldown. logic high to enable bridge b. internal benbl 22 i bridge b enable pulldown. logic high sets bout1 high, bout2 low. bphase 23 i bridge b phase (direction) internal pulldown. bi0 26 i sets bridge b current: 00 = 100%, bridge b current set 01 = 71%, 10 = 38%, 11 = 0 bi1 27 i internal pulldown. low = slow decay, open = mixed decay, decay 19 i decay mode high = fast decay. internal pulldown and pullup. active-low reset input initializes internal logic nreset 16 i reset input and disables the h-bridge outputs. internal pulldown. logic high to enable device, logic low to enter nsleep 17 i sleep mode input low-power sleep mode. internal pulldown. avref 12 i bridge a current set reference input reference voltage for winding current set. can be driven individually with an external dac for microstepping, or tied to a reference bvref 13 i bridge b current set reference input (e.g., v3p3out). status logic low when in fault condition (overtemp, nfault 18 od fault overcurrent) output isena 6 io bridge a ground / isense connect to current sense resistor for bridge a isenb 9 io bridge b ground / isense connect to current sense resistor for bridge b aout1 5 o bridge a output 1 connect to motor winding a aout2 7 o bridge a output 2 bout1 10 o bridge b output 1 connect to motor winding b bout2 8 o bridge b output 2 (1) directions: i = input, o = output, oz = tri-state output, od = open-drain output, io = input/output copyright ? 2010 C 2011, texas instruments incorporated 3
DRV8813 slvsa72c C april 2010 C revised may 2011 www.ti.com absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) value unit vmx power supply voltage range C 0.3 to 47 v digital pin voltage range C 0.5 to 7 v vref input voltage C 0.3 to 4 v isensex pin voltage C 0.3 to 0.8 v peak motor drive output current, t < 1 s internally limited a continuous motor drive output current (3) 2.5 a continuous total power dissipation see dissipation ratings table t j operating virtual junction temperature range C 40 to 150 c t a operating ambient temperature range C 40 to 85 c t stg storage temperature range C 60 to 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute C maximum C rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) power dissipation and thermal limits must be observed. 4 copyright ? 2010 C 2011, texas instruments incorporated
DRV8813 www.ti.com slvsa72c C april 2010 C revised may 2011 thermal information DRV8813 thermal metric (1) pwp units 28 pins ja junction-to-ambient thermal resistance (2) 31.6 jctop junction-to-case (top) thermal resistance (3) 15.9 jb junction-to-board thermal resistance (4) 5.6 c/w jt junction-to-top characterization parameter (5) 0.2 jb junction-to-board characterization parameter (6) 5.5 jcbot junction-to-case (bottom) thermal resistance (7) 1.4 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . (2) the junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a jedec-standard, high-k board, as specified in jesd51-7, in an environment described in jesd51-2a. (3) the junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. no specific jedec-standard test exists, but a close description can be found in the ansi semi standard g30-88. (4) the junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the pcb temperature, as described in jesd51-8. (5) the junction-to-top characterization parameter, jt , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining ja , using a procedure described in jesd51-2a (sections 6 and 7). (6) the junction-to-board characterization parameter, jb , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining ja , using a procedure described in jesd51-2a (sections 6 and 7). (7) the junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. no specific jedec standard test exists, but a close description can be found in the ansi semi standard g30-88. recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v m motor power supply voltage range (1) 8.2 45 v v ref vref input voltage (2) 1 3.5 v i v3p3 v3p3out load current 0 1 ma f pwm externally applied pwm frequency 0 100 khz (1) all v m pins must be connected to the same supply voltage. (2) operational at vref between 0 v and 1 v, but accuracy is degraded. electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit power supplies i vm vm operating supply current v m = 24 v, f pwm < 50 khz 5 8 ma i vmq vm sleep mode supply current v m = 24 v 10 20 a v uvlo vm undervoltage lockout voltage v m rising 7.8 8.2 v v3p3out regulator v 3p3 v3p3out voltage iout = 0 to 1 ma 3.2 3.3 3.4 v logic-level inputs v il input low voltage 0.6 0.7 v v ih input high voltage 2.2 5.25 v v hys input hysteresis 0.3 0.45 0.6 v i il input low current vin = 0 C 20 20 a i ih input high current vin = 3.3 v 100 a r pd internal pulldown resistance 100 k copyright ? 2010 C 2011, texas instruments incorporated 5
DRV8813 slvsa72c C april 2010 C revised may 2011 www.ti.com electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit nfault output (open-drain output) v ol output low voltage i o = 5 ma 0.5 v i oh output high leakage current v o = 3.3 v 1 a decay input v il input low threshold voltage for slow decay mode 0 0.8 v v ih input high threshold voltage for fast decay mode 2 v i in input current 40 a r pu internal pullup resistance (to 3.3 v) 130 k r pd internal pulldown resistance 80 k h-bridge fets v m = 24 v, i o = 1 a, t j = 25 c 0.2 hs fet on resistance v m = 24 v, i o = 1 a, t j = 85 c 0.25 0.32 r ds(on) ? v m = 24 v, i o = 1 a, t j = 25 c 0.2 ls fet on resistance v m = 24 v, i o = 1 a, t j = 85 c 0.25 0.32 i off off-state leakage current C 20 20 a motor driver internal current control pwm f pwm 50 khz frequency t blank current sense blanking time 3.75 s t r rise time 30 200 ns t f fall time 30 200 ns protection circuits i ocp overcurrent protection trip level 3 a t tsd thermal shutdown temperature die temperature 150 160 180 c current control i ref xvref input current xvref = 3.3 v C 3 3 a xvref = 3.3 v, 100% current setting 635 660 685 v trip xisense trip voltage xvref = 3.3 v, 71% current setting 445 469 492 mv xvref = 3.3 v, 38% current setting 225 251 276 a isense current sense amplifier gain reference only 5 v/v 6 copyright ? 2010 C 2011, texas instruments incorporated
DRV8813 www.ti.com slvsa72c C april 2010 C revised may 2011 functional description pwm motor drivers the DRV8813 contains two h-bridge motor drivers with current-control pwm circuitry. a block diagram of the motor control circuitry is shown in figure 1 . a bipolar stepper motor is shown, but the drivers can also drive two separate dc motors. figure 1. motor control circuitry note that there are multiple vm motor power supply pins. all vm pins must be connected together to the motor supply voltage. copyright ? 2010 C 2011, texas instruments incorporated 7
DRV8813 slvsa72c C april 2010 C revised may 2011 www.ti.com bridge control the xphase input pins control the direction of current flow through each h-bridge. the xenbl input pins enable the h-bridge outputs when active high. table 2 shows the logic. table 2. h-bridge logic xenbl xphase xout1 xout2 0 x z z 1 1 h l 1 0 l h the control inputs have internal pulldown resistors of approximately 100 k . current regulation the current through the motor windings is regulated by a fixed-frequency pwm current regulation, or current chopping. when an h-bridge is enabled, current rises through the winding at a rate dependent on the dc voltage and inductance of the winding. once the current hits the current chopping threshold, the bridge disables the current until the beginning of the next pwm cycle. for stepping motors, current regulation is normally used at all times, and can changing the current can be used to microstep the motor. for dc motors, current regulation is used to limit the start-up and stall current of the motor. if the current regulation feature is not needed, it can be disabled by connecting the xisense pins directly to ground and connecting the xvref pins to v3p3. the pwm chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xisen pins, multiplied by a factor of 5, with a reference voltage. the reference voltage is input from the xvref pins, and is scaled by a 2-bit dac that allows current settings of 100%, 71%, 38% of full-scale, plus zero. the full-scale (100%) chopping current is calculated in equation 1 . (1) example: if a 0.25- ? sense resistor is used and the vrefx pin is 2.5 v, the full-scale (100%) chopping current will be 2.5 v / (5 x 0.25 ? ) = 2 a. two input pins per h-bridge (xi1 and xi0) are used to scale the current in each bridge as a percentage of the full-scale current set by the vref input pin and sense resistance. the xi0 and xi1 pins have internal pulldown resistors of approximately 100 k . the function of the pins is shown in table 3 . table 3. h-bridge pin functions relative current xi1 xi0 (% full-scale chopping current) 1 1 0% (bridge disabled) 1 0 38% 0 1 71% 0 0 100% note that when both xi bits are 1, the h-bridge is disabled and no current flows. example: if a 0.25- ? sense resistor is used and the vref pin is 2.5 v, the chopping current will be 2 a at the 100% setting (xi1, xi0 = 00). at the 71% setting (xi1, xi0 = 01) the current will be 2 a x 0.71 = 1.42 a, and at the 38% setting (xi1, xi0 = 10) the current will be 2 a x 0.38 = 0.76 a. if (xi1, xi0 = 11) the bridge will be disabled and no current will flow. 8 copyright ? 2010 C 2011, texas instruments incorporated i = chop v refx 5 r isense ?
DRV8813 www.ti.com slvsa72c C april 2010 C revised may 2011 decay mode during pwm current chopping, the h-bridge is enabled to drive current through the motor winding until the pwm current chopping threshold is reached. this is shown in figure 2 as case 1. the current flow direction shown indicates the state when the xenbl pin is high. once the chopping current threshold is reached, the h-bridge can operate in two different states, fast decay or slow decay. in fast decay mode, once the pwm chopping current level has been reached, the h-bridge reverses state to allow winding current to flow in a reverse direction. as the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. fast decay mode is shown in figure 2 as case 2. in slow decay mode, winding current is re-circulated by enabling both of the low-side fets in the bridge. this is shown in figure 2 as case 3. figure 2. decay mode the DRV8813 supports fast decay, slow decay and a mixed decay mode. slow, fast, or mixed decay mode is selected by the state of the decay pin - logic low selects slow decay, open selects mixed decay operation, and logic high sets fast decay mode. the decay pin has both an internal pullup resistor of approximately 130 k and an internal pulldown resistor of approximately 80 k . this sets the mixed decay mode if the pin is left open or undriven. note that the decay pin sets the decay mode for both h-bridges. mixed decay mode begins as fast decay, but at a fixed period of time (75% of the pwm cycle) switches to slow decay mode for the remainder of the fixed pwm period. blanking time after the current is enabled in an h-bridge, the voltage on the xisen pin is ignored for a fixed period of time before enabling the current sense circuitry. this blanking time is fixed at 3.75 s. note that the blanking time also sets the minimum on time of the pwm. copyright ? 2010 C 2011, texas instruments incorporated 9
DRV8813 slvsa72c C april 2010 C revised may 2011 www.ti.com nreset and nsleep operation the nreset pin, when driven active low, resets the internal logic. it also disables the h-bridge drivers. all inputs are ignored while nreset is active. driving nsleep low will put the device into a low power sleep state. in this state, the h-bridges are disabled, the gate drive charge pump is stopped, the v3p3out regulator is disabled, and all internal clocks are stopped. in this state all inputs are ignored until nsleep returns inactive high. when returning from sleep mode, some time (approximately 1 ms) needs to pass before the motor driver becomes fully operational. note that nreset and nsleep have internal pulldown resistors of approximately 100 k . these signals need to be driven to logic high for device operation. protection circuits the DRV8813 is fully protected against undervoltage, overcurrent and overtemperature events. overcurrent protection (ocp) an analog current limit circuit on each fet limits the current through the fet by removing the gate drive. if this analog current limit persists for longer than the ocp time, all fets in the h-bridge will be disabled and the nfault pin will be driven low. the device will remain disabled until either nreset pin is applied, or vm is removed and re-applied. overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. note that overcurrent protection does not use the current sense circuitry used for pwm current control, and is independent of the i sense resistor value or vref voltage. thermal shutdown (tsd) if the die temperature exceeds safe limits, all fets in the h-bridge will be disabled and the nfault pin will be driven low. once the die temperature has fallen to a safe level operation will automatically resume. undervoltage lockout (uvlo) if at any time the voltage on the vm pins falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled and internal logic will be reset. operation will resume when v m rises above the uvlo threshold. 10 copyright ? 2010 C 2011, texas instruments incorporated
DRV8813 www.ti.com slvsa72c C april 2010 C revised may 2011 thermal information thermal protection the DRV8813 has thermal shutdown (tsd) as described above. if the die temperature exceeds approximately 150 c, the device will be disabled until the temperature drops to a safe level. any tendency of the device to enter tsd is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. power dissipation power dissipation in the DRV8813 is dominated by the power dissipated in the output fet resistance, or r ds(on) . average power dissipation when running a stepper motor can be roughly estimated by equation 2 . (2) where p tot is the total power dissipation, r ds(on) is the resistance of each fet, and i out(rms) is the rms output current being applied to each winding. i out(rms) is equal to the approximately 0.7x the full-scale output current setting. the factor of 4 comes from the fact that there are two motor windings, and at any instant two fets are conducting winding current for each winding (one high-side and one low-side). the maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking. note that r ds(on) increases with temperature, so as the device heats, the power dissipation increases. this must be taken into consideration when sizing the heatsink. heatsinking the powerpad ? package uses an exposed pad to remove heat from the device. for proper operation, this pad must be thermally connected to copper on the pcb to dissipate heat. on a multi-layer pcb with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. on pcbs without internal planes, copper area can be added on either side of the pcb to dissipate heat. if the copper area is on the opposite side of the pcb from the device, thermal vias are used to transfer the heat between top and bottom layers. for details about how to design the pcb, refer to ti application report slma002 , " powerpad ? thermally enhanced package" and ti application brief slma004 , " powerpad ? made easy", available at www.ti.com . in general, the more copper area that can be provided, the more power can be dissipated. copyright ? 2010 C 2011, texas instruments incorporated 11 p = r (i ) tot ds(on) out(rms) 4 2
package option addendum www.ti.com 18-may-2011 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) DRV8813pwp active htssop pwp 28 50 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr DRV8813pwpr active htssop pwp 28 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant DRV8813pwpr htssop pwp 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 q1 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) DRV8813pwpr htssop pwp 28 2000 367.0 367.0 38.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2

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